1. Technical Field
Embodiments of the present disclosure relate generally to de-coupling capacitors, and more specifically to a capacitor cell supporting circuit operation at higher-voltages while employing capacitors designed for lower voltages.
2. Related Art
Both integrated circuit capacitors and conventional parallel plate capacitors have voltage rating specifying the maximum voltage that can be applied across their terminals without causing damage to the capacitor structure. Integrated circuit capacitors are often implemented using a metal-oxide-semiconductor (MOS) transistor structure, fabricated using corresponding fabrication processes. Typically, the gate-oxide thickness is determined by the fabrication process, and may be designed to target a specific operational environment, such as for example, operation with low-voltage power supplies. One example of a MOS capacitor fabrication process is a 1.8V fabrication process, in which the gate oxide of the MOS capacitor is designed to withstand a maximum voltage across it of 1.8V.
Capacitors often need to be employed in circuits that operate from power supply voltages that are greater than the maximum safe voltage that can be applied across the capacitors. An example is an input-output (I/O) circuit that can selectively be chosen to operate from a 1.8V power supply and a 3.3V power supply, and which is power-supply-decoupled by a decoupling capacitor fabricated to withstand a maximum of only 1.8V across its terminals. In such circuits, it may need to be ensured that the use of capacitors designed for lower voltages can reliably support circuit operation at higher voltages, i.e., without damage to the capacitors.